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VLSI Design - 45 Days Internship Training Program

Join 45 Days VLSI Design Internship Training Program at NextVision Infotech. Learn Verilog, RTL, verification, synthesis, FPGA. ₹649 only with certificate.

45 Days
Anywhere in India • Patna • (Offline & Online)
INT-ECE-VLSI-45D
₹649
₹1,299 Save 50%
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Program Description

NextVision Infotech presents a comprehensive VLSI Design Internship Training Program spanning 45 days. This intensive program is designed for engineering students across all disciplines - B.Tech, B.E., Diploma, Polytechnic, B.Sc., and other technical streams - who want to build a strong foundation in VLSI design and verification. The program covers the complete VLSI design lifecycle from digital electronics fundamentals to chip design and verification. Students will learn digital electronics, CMOS technology, Verilog HDL, VHDL, combinational and sequential circuit design, FSM design, RTL design, verification, synthesis, and FPGA implementation. Over six weeks, the program progresses from fundamentals to advanced VLSI design. Week 1 introduces VLSI fundamentals and digital electronics. Week 2 covers Verilog HDL. Week 3 focuses on combinational and sequential circuit design. Week 4 covers FSM and RTL design. Week 5 is dedicated to verification, synthesis, FPGA, and live projects. Week 6 covers documentation, viva, and certification. The program follows industry-standard workflows used by professional VLSI engineers across India. Students work on real VLSI projects using Verilog, VHDL, ModelSim, Xilinx Vivado, Cadence, and Synopsys, prepare RTL code, testbenches, and complete documentation. The curriculum draws inspiration from premier engineering institutions across India and follows professional VLSI standards used in semiconductor industry. Students gain practical skills that prepare them for careers in VLSI design, verification, physical design, and semiconductor technology. This program is delivered both online and offline, allowing students from any state or city across India to enroll and benefit. The institute is ISO 9001:2015 certified, and the internship certificate is accepted by universities, colleges, and companies throughout the country. Upon successful completion, students receive an Internship Certificate, Industrial Training Certificate, Project Completion Certificate, and an Offer Letter. Learning outcomes include mastering digital design, Verilog HDL, RTL design, verification, synthesis, and FPGA implementation.

Skills You'll Learn

VLSI Design
Digital Electronics
Verilog HDL
VHDL
RTL Design
FSM Design
Testbench
Verification
Synthesis
Static Timing Analysis
FPGA
Xilinx Vivado
ModelSim
Cadence
Synopsys
SystemVerilog
UVM

Projects You'll Work On

Complete VLSI Design Project

Students will complete a full VLSI design project including RTL design using Verilog, testbench creation, functional verification, synthesis, timing analysis, FPGA implementation, and complete project documentation as per industry standards.

Program Modules

1

W1: Week 1: VLSI Fundamentals and Digital Electronics

Introduction to VLSI, VLSI design flow, Moore law, scaling, ASIC vs FPGA, full custom, semi-custom, standard cell, gate array, digital electronics fundamentals, number systems, Boolean algebra, logic gates, combinational logic, sequential logic, latches, flip-flops, SR flip-flop, JK flip-flop, D flip-flop, T flip-flop, registers, counters, shift registers, memory - RAM, ROM, SRAM, DRAM, CMOS technology, NMOS, PMOS, CMOS inverter, CMOS logic gates, transmission gates, pass transistor logic, dynamic logic, power dissipation, low power design.

2

W2: Week 2: Verilog HDL

Introduction to Verilog HDL, Verilog vs VHDL, module structure, ports, data types - wire, reg, integer, real, time, parameters, operators, continuous assignment, procedural blocks - always, initial, blocking vs non-blocking assignments, conditional statements, case statements, loops, tasks, functions, system tasks, compiler directives, timing controls, delay modeling, gate-level modeling, dataflow modeling, behavioral modeling, structural modeling, module instantiation, port connections, hierarchical design.

3

W3: Week 3: Combinational and Sequential Circuit Design

Combinational circuit design - adders, half adder, full adder, ripple carry adder, carry look ahead adder, subtractors, multipliers, multiplexers, demultiplexers, encoders, decoders, comparators, parity generators, code converters, sequential circuit design - latches, flip-flops, registers, shift registers, counters, synchronous counters, asynchronous counters, ring counters, Johnson counters, up-down counters, modulo counters, clock dividers, frequency dividers, memory design - RAM, ROM, FIFO, LIFO.

4

W4: Week 4: FSM and RTL Design

Finite state machine (FSM), Moore machine, Mealy machine, state diagrams, state tables, state encoding, binary encoding, gray encoding, one-hot encoding, FSM design, sequence detector, traffic light controller, vending machine, elevator controller, UART, SPI, I2C, RTL design, register transfer level, data path design, control path design, ASM charts, algorithmic state machine, pipelining, retiming, RTL coding guidelines, synthesis-friendly coding.

5

W5: Week 5: Verification, Synthesis, FPGA, and Live Projects

Verification fundamentals, testbench creation, stimulus generation, response checking, self-checking testbench, directed testing, random testing, functional coverage, code coverage, assertion-based verification, SystemVerilog basics, UVM overview, synthesis, synthesis flow, synthesis tools - Xilinx Vivado, Cadence Genus, Synopsys Design Compiler, synthesis constraints, timing analysis, static timing analysis (STA), setup time, hold time, clock skew, clock tree synthesis, FPGA architecture, FPGA design flow, FPGA implementation, bitstream generation, FPGA boards - Xilinx, Altera, Lattice, live projects - ALU, UART, SPI, I2C, FIFO, traffic light controller, complete documentation.

6

W6: Week 6: Documentation, Viva, and Certification

Project documentation, RTL documentation, testbench documentation, verification report, synthesis report, timing report, FPGA implementation report, project report preparation, resume building, interview preparation, viva-voce examination, feedback session, certificate distribution.

Key Features

45 Days Comprehensive Training
Industry-Standard Curriculum
Live VLSI Projects
Professional Documentation
ISO 9001:2015 Certified Institute
Offer Letter Provided
Internship Certificate Included
Industrial Training Certificate
Project Report Guidance
Viva-Voce Preparation
Online & Offline Mode
Pan-India Enrollment

What You'll Learn

Master VLSI fundamentals and digital electronics
Program in Verilog HDL
Design combinational and sequential circuits
Design finite state machines
Apply RTL design methodologies
Verify designs using testbenches
Perform synthesis and timing analysis
Implement designs on FPGA
Build a professional VLSI portfolio
Prepare for VLSI design jobs across India

Examination Details

Exam NameFull MarksPass Marks
Module-wise Assessment10040
Project Evaluation10050
Final Presentation5025
Viva-Voce5025
VLSI Design - 45 Days Internship Training Program

Internship Details

Duration45 Days
LocationAnywhere in India • Patna • (Offline & Online)
Available Seats100
Course CodeINT-ECE-VLSI-45D
Apply Now — ₹649

Prerequisites

  • Pursuing or completed B.Tech/B.E./Diploma in Electronics, ECE, EEE, or related field
  • Basic knowledge of digital electronics
  • Basic knowledge of programming
  • Interest in VLSI design

Who Can Enroll ?

  • B.Tech ECE students (1st to 8th semester)
  • B.E. ECE students
  • B.Tech Electronics Engineering students
  • B.Tech Electrical Engineering students
  • Diploma Electronics students (1st to 6th semester)
  • Polytechnic students
  • Working professionals wanting to upskill
  • Students from all over India seeking practical training

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